1. Field of the Invention
The present invention relates to a spread spectrum clock generator (SSGC).
2. Description of the Related Art
In the art of a clock generator a spread spectrum clock generator (SSGC) is known. It aims to prevent electromagnetic interference (EMI) having a peak at a specific frequency by slightly modulating the frequency of a clock signal to spread the EMI energy to reduce a peak value. Japanese Patent Application Publication No. 2004-328280 and No. 2007-288375 disclose, as such an SSCG, a PLL (Phase Locked Loop) circuit or a fractional PLL circuit with a division ratio of a rational number, for example.
FIG. 17 is a block diagram of a conventional spread spectrum clock generator as a fractional PLL circuit. A reference clock signal ref_ck generated by a not-shown clock generator is divided by an input frequency divider 11 to an input clock signal comp_ck and input to a phase frequency comparator 21. The phase frequency comparator 21 detects a phase difference between the input clock signal comp_ck and a feedback signal fb_ck and outputs it to a charge pump 22. The charge pump 22 increases or decreases a charge pump voltage in accordance with the phase difference and outputs it to a loop filter 23. The loop filter 23 outputs a control voltage in accordance with the charge pump voltage to a voltage controlled oscillator (VCO) 24 which includes a V/I converter 24a to covert the control voltage to a control current, a current DA converter (IDAC) 24b to generate a control current spread-spectrum (SS) modulated under a spread spectrum controller 25, and a current controlled oscillator 24c to generate and output an output clock signal vco_ck with a frequency and a phase based on the SS modulated control current. The output clock signal vco_ck is divided for use in other circuits by an output frequency divider 12. Herein, a signal divided by the frequency divider 12 is referred to as a pixel clock signal to be used in an image processor. The output clock signal vco_ck is divided by a frequency divider 26 and input to the phase frequency comparator 21 as a feedback signal fb_ck. The division ratio of the frequency divider 26 is cyclically switched between an integer N and an integer N+1 in accordance with the count value of an accumulator 27 which counts the input clock signal comp_ck. The fractional PLL circuit performs a negative feedback control so that the feedback signal fb_ck and the input clock signal comp_ck coincide with each other in phase and frequency. Also, it realizes a decimal division ratio between the integers N and N+1 on average by switching the division ratio of the frequency divider 26.
The spread spectrum modulation of the current DA converter 24b is described with reference to FIG. 18. By SS modulation, the frequency of the output clock signal vco_ck is varied in a modulation cycle ssint over the range of a maximal value fmax and a minimal value fmin around a certain frequency fc. The modulation level ss_amp indicating a maximal variation rate of the frequency of the output clock signal vco_ck is set in the spread spectrum controller 25. The modulation level is an integer from zero to 31 and the maximal variation rate is represented by ss_amp/1,024(%). For example, at ss_amp=31, the maximal and minimal values fmax, fmin of the frequency of the output clock signal vco_ck are increased and decreased by about 3.1% from the center frequency fc, respectively. The spread spectrum controller 25 generates SS modulation waveform data ddsd_org to change the control current in the current DA converter 24b and change the frequency of the output clock signal vco_ck within the range of the maximal variation rates. The SS modulation waveform data is an integer from zero to 255 for example, and the maximal value 255 corresponds to the maximal frequency fmax, the minimal value zero corresponds to the minimal frequency fmin and the value 128 corresponds to the center frequency fc or no change in frequency.
In the following an example of calculation of the SS modulation waveform data ddsd_org when a frequency variation in the output clock signal vco_ck takes triangular waveform is described. A count value count(n) incrementing to count clocks of a pixel clock signal pix_ck is used to calculate the SS modulation waveform data ddsd_org, for example. A step size Δcount of the count value, the initial value count (0), and the count value count(n) are expressed by the following equations.Δcount=2*255/ssint  (1)count(0)=0  (2)count(n)=count(n−1)+Δcount, 1≦n≦ssint−1  (3)
The count value count (n) increments by the step size Δcount over a modulation cycle ssint. The SS modulation waveform data ddsd_org is calculated as follows:
                                          When            ⁢                                                  ⁢            0                    ≤                      int            ⁢                                                  ⁢                          (                              count                ⁡                                  (                  n                  )                                            )                                <          128                ,                  ddsd_org          =                      128            +                          int              ⁢                                                          ⁢                              (                                  count                  ⁡                                      (                    n                    )                                                  )                                                                        (        4        )                                                      When            ⁢                                                  ⁢            128                    ≤                      int            ⁢                                                  ⁢                          (                              count                ⁡                                  (                  n                  )                                            )                                <          383                ,                  ddsd_org          =                                    255              -                              {                                                      int                    ⁢                                                                                  ⁢                                          (                                              count                        ⁡                                                  (                          n                          )                                                                    )                                                        -                  127                                }                                      =                          382              -                              int                ⁢                                                                  ⁢                                  (                                      count                    ⁡                                          (                      n                      )                                                        )                                                                                        (        5        )                                                      When            ⁢                                                  ⁢            383                    ≤                      int            ⁢                                                  ⁢                          (                              count                ⁡                                  (                  n                  )                                            )                                <          510                ,                  ddsd_org          =                                    128              +                              {                                                      int                    ⁢                                                                                  ⁢                                          (                                              count                        ⁡                                                  (                          n                          )                                                                    )                                                        -                                      (                                                                  2                        *                        255                                            -                      0                                        )                                                  }                                      =                                          int                ⁢                                                                  ⁢                                  (                                      count                    ⁡                                          (                      n                      )                                                        )                                            -              382                                      ,                  where          ⁢                                          ⁢          int          ⁢                                          ⁢                      (                          count              ⁡                              (                n                )                                      )                    ⁢                                          ⁢          is          ⁢                                          ⁢          an          ⁢                                          ⁢          integer          ⁢                                          ⁢          portion          ⁢                                          ⁢          of          ⁢                                          ⁢          the          ⁢                                          ⁢          count          ⁢                                          ⁢          value          ⁢                                          ⁢                                    count              ⁡                              (                n                )                                      .                                              (        6        )            
The current DA converter 24b varies the control current for the current controlled oscillator 24c on the basis of the SS modulation waveform data ddsd_org and varies the frequency of the output clock signal vco_ck within the range of the maximal variation rates represented by the modulation level ss_amp.
For the purpose of improving the amplitude accuracy of SS modulation, the current DA converter 24b can use a part of the control current of the current controlled oscillator 24c as a reference current to track the amplitude of the SS modulation waveform to the mean frequency or center frequency fc of the output clock signal vco_ck.
Thus, in the conventional SSCG the current DA converter 24b generates SS modulated control current and directly varies the oscillation frequency of the current controlled oscillator 24c by the control current. Therefore, the loop response of the PLL circuit has to be at sufficiently low speed relative to the SS modulation cycle ssint. Because of this, it faces a problem that due to the narrow bandwidth of the loop filter 23, a system correction amount to deal with a fluctuation cannot be large, which causes deterioration in jitter characteristic.
Another problem is that the conventional SSCG can vary the frequency only on a pixel clock signal basis so that fine frequency variation cannot be realized.
Another problem is that in the fractional PLL circuit phase mismatches occur in changing the division ratio of the frequency divider 26. This causes spurious components to enter the output clock signal vco_ck and deteriorate the jitter characteristic of the output clock signal vco_ck.
Furthermore, the conventional fractional PLL circuit requires a large division ratio N of the frequency divider 26 in order to increase multiplied frequency resolution, so that the frequency of the signals input to the phase frequency comparator 21 cannot be increased and the loop bandwidth of the fractional PLL circuit cannot be broadened either. This increases the phase noise in the voltage controlled oscillator 24a and degrades jitter characteristic.